The present invention relates to baseband systems and, more particularly, to the mutual time alignment of multiple wireless links in a MIMO (multiple in, multiple out) base station.
In a conventional MIMO cellular communications network, a base station has a number of antennas and electronic equipment to support the operations of those antennas, where each antenna can receive incoming (i.e., uplink) signals from wireless UE (user equipment) devices and transmit outgoing (i.e., downlink) signals to the UEs.
In certain conventional base stations, the electronic equipment includes (a) a baseband digital front-end (BDFE) processor that performs baseband signal processing on digital versions of the incoming and outgoing signals, (b) one or more radio frequency integrated circuit (RFIC) transceiver chips comprising (i) digital-to-analog converters (DACs) that convert outgoing digital signals into outgoing analog signals and (ii) analog-to-digital converters (ADCs) that convert incoming analog signals into incoming digital signals, and (c) power amplifiers, one for each antenna, that amplify the outgoing analog signals to be transmitted by the antennas.
In certain conventional implementations, each RFIC chip can be configured to support a maximum number of different antennas, where the BDFE processor and each RFIC chip communicate with each other over bi-directional, duplexed, JESD communication links that conform to the Joint Electron Device Engineering Council (JEDEC) Serial Interface for Data Converters standard (Document JESD204B.01, January 2012), the teachings of which are incorporated herein by reference, where there is one JESD link for each antenna. Thus, for an RFIC chip that supports up to four different antennas, there will be four JESD links between that RFIC chip and the BDFE processor.
To support communications over the JESD links, the BDFE processor has a JESD-compliant interface comprising a JESD transmitter (TX) and a JESD receiver (RX) for each JESD link with an RFIC chip, and each RFIC chip also has a JESD-compliant interface comprising a JESD TX and a JESD RX for each JESD link with the BDFE processor. Each JESD RX (in either the BDFE processor or in an RFIC chip) is able to detect an out-of-sync condition in the data that the JESD RX receives over the corresponding JESD link. Thus, a JESD RX in the BDFE processor is able to detect an out-of-sync condition in the data that that JESD RX receives from the corresponding JESD TX in the corresponding RFIC chip over the corresponding JESD link. Similarly, the corresponding JESD RX in that same corresponding RFIC chip is able to detect an out-of-sync condition in the data that that JESD RX receives from the corresponding JESD TX in the BDFE processor over that same corresponding JESD link.
According to the JESD standard, for two nodes (e.g., a BDFE processor and an RFIC chip) communicating over a JESD link, the first node transmits a sync signal to the second node indicating whether the JESD RX in the first node has determined that the corresponding JESD link is in sync (i.e., sync signal high) or out of sync (i.e., sync signal low). Similarly, the second node transmits a sync signal to the first node indicating whether the JESD RX in the second node has determined that the same JESD link is in sync or out of sync.
If, for example, the first node receives a sync signal indicating that the JESD link is out of sync, then the first node responds by transmitting a data signal having a fixed data pattern over the JESD link to the second node to enable the second node to re-synchronize the JESD link. During that re-synchronization process, the transmission of real user data from the first node to the second node over that JESD link is interrupted. After the re-synchronization process is complete, the second node will transmit a sync signal to the first node indicating that the JESD link is back in sync, and the first node can then resume the transmission of real user data to the second node over the JESD link.
In some conventional MIMO base stations, the antennas can be configured in different ways at different times to support different communications. For example, at any given time, one or more subsets of the antennas can be configured into one or more logical groups to support communications with the UEs. In order to ensure that (i) the outgoing signals will be able to be successfully processed at the UEs and that (ii) the incoming signals will be able to be successfully processed at the base station, the different signal processing paths (also referred to herein as “lanes”) associated with the different antennas in a logical group need to be mutually aligned in time.
Note that, as used in this specification, the terms “synchronization” and “in sync” refer to the timing within a single processing path, such as within a single JESD link, while the terms “time alignment” and “aligned in time” refer to the relative timing between different signal processing paths, such as between multiple JESD links. In general, two or more JESD links can be individually in sync and still not be mutually aligned in time with each other. For successful communications, the JESD links for a logical group of antennas should be both individually in sync as well as mutually aligned in time.
If one of the JESD links in a logical group becomes out of sync, then the processing of real user data is suspended, and all of the JESD links in that logical group should be individually re-synchronized and mutually re-aligned in time before the processing of real user data is resumed. Similarly, if one or more additional antennas are added to an existing logical group, then again the processing of real user data is suspended, and all of the JESD links in that augmented logical group should be individually re-synchronized and mutually re-aligned in time before the processing of real user data is resumed.
In conventional JESD-compliant MIMO base stations, the process of synchronizing and time aligning multiple JESD links is controlled by software executed by the BDFE processor using a time-based generator module. One such solution is described in U.S. Pat. No. 8,964,791, the teachings of which are incorporated herein by reference in their entirety. Unfortunately, the latency associated with this software-based solution is undesirably long. Moreover, the software-based solution involves general-purpose processor interrupts which can be unpredictable and therefore non-deterministic.